View MB81ES123245-10_5210293.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-11440-2e fujitsu semiconductor data sheet copyright?2006 fujitsu li mited all rights reserved memory cmos 128 m-bit (4-bank 1 m-word 32-bit) single data rate i/f fcram tm consumer/embedded application specific memory for sip MB81ES123245-10 description the fujitsu mb81es123245 is a single data rate in terface fast cycle random access memory (fcram*) containing 134,217,728 memory cells accessible in a 32 -bit format. the mb81es123245 features a fully synchro- nous operation referenced to a positive clock edge whereby all operations are synchroni zed at a clock input which enables high performance and simple user interface coexistence. the mb81es123245 is utilized using a fujitsu advanced fc ram core technology and designed for low power consumption and low voltage operation than regular synchronous dram (sdram) . the mb81es123245 is dedicated for sip (system in a package) , and ideally suited for various embedded/ consumer applications including digital avs and im age processing where a large band width and low power consumption memory is needed. * : fcram is a trademark of fujitsu limited, japan. product lineup parameter MB81ES123245-10 clock frequency (max) cl = 2 54 mhz cl = 3108 mhz burst mode cycle time (min) cl = 2 18.5 ns cl = 3 9.2 ns access time from clk (max) cl = 29 ns cl = 37 ns operating current (max) (64 page length) 35 ma power down mode current (max) (i dd2ps ) 0.5 ma self-refresh current (max) tj = + 35 c max 200 a
MB81ES123245-10 2 features ?1 m word 32 bit 4 banks organization low power supply - v dd : + 1.7 v to + 1.9 v - v ddq : + 1.7 v to + 1.9 v 1.8v cmos i/o interface 4 k refresh cycles every 64 ms auto- and self-refresh four banks operation programmable burst type, bu rst length, and cas latency burst read/write operation and burst read/single write operation capability programmable page length function programmable partial array self-refresh (pasr) programmable driver strength (ds) deep power down mode junction temperature (tj) : ? 25 c to + 95 c cke power down mode output enable and input data mask self burn-in function for test built in self test (bist) function for test
MB81ES123245-10 3 pad layout pad no. 74 mb81es123245 pad no. 75 pad no. 1 pad no.138 pad no.75 v dd v ss ? ? ? ? ? ? ? ? ? dq 23 ? dq 22 ? ? dq 20 ? dq 21 ? ? dq 19 ? dq 18 v ddq v ssq dq 16 ? dq 17 ? ? dqm 1 ? dqm 0 v dd v ss dqm 2 ? dqm 3 ? ? dq 25 ? dq 24 v ssq v ddq dq 26 ? dq 27 ? ? dq 29 ? dq 28 ? ? dq 30 ? dq 31 ? ? ? v ss v dd pad no.138 pad no.1 v dd v ss ? v ss ? ? ? dq 15 ? dq 14 ? ? dq 12 ? dq 13 ? ? dq 11 ? dq 10 v ddq v ssq dq 8 ? dq 9 ? a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 v ss v dd cke clk csb rasb casb web ba 0 ba 1 a 11 a 12 a 13 v ss ? dq 1 ? dq 0 v ssq v ddq dq 2 ? dq 3 ? ? dq 5 ? dq 4 ? ? dq 8 ? dq 7 ? v ss v ss v dd pad no.74
MB81ES123245-10 4 pad descriptions * : a 12 must be connected to v ss in 256 page length mode. a 13 must be connected to v ss in 256 page length mode and 128 page length mode. symbol function v ddq , v dd supply voltage dq 31 to dq 0 data i/o v ssq , v ss ground we (web) write enable cas (casb) column address strobe ras (rasb) row address strobe cs (csb) chip select ba 1 , ba 0 bank select (bank address) ap auto precharge enable a 13 to a 0 * address input row column 256 page a 11 to a 0 a 7 to a 0 128 page a 12 to a 0 a 6 to a 0 64 page a 13 to a 0 a 5 to a 0 cke clock enable clk clock input dqm 3 to dqm 0 input mask/output enable ? don?t bond
MB81ES123245-10 5 block diagram cke clk ras cas we dqm 3 to dqm 0 dq 31 to dq 0 a 9 to a 0 , a 10 /ap, a 13 to a 11 cs ras cas we ba 1 , ba 0 i/o v dd v ssq v ss v ddq mode register fcram core (1,048,576 32) address buffer/ register col. address row address i/o data buffer/ register column address counter clock buffer command decoder control signal latch bank-1 bank-0 bank-3 bank-2 to each block
MB81ES123245-10 6 functional truth table * 1 1. command truth table * 2 , * 3 , * 4 *1 : v = valid, l = v il , h = v ih , x = either v il or v ih . row address 256 page length : a 11 to a 0 128 page length : a 12 to a 0 64 page length : a 13 to a 0 column address 256 page length : a 7 to a 0 128 page length : a 6 to a 0 64 page length : a 5 to a 0 *2 : all commands assume no csus comm and on previous rising edge of clock. *3 : all commands are assumed to be valid state transitions. *4 : all inputs are latched on the rising edge of clock. *5 : nop and desl commands have th e same effect. unless specifically noted, nop will represent both nop and desl command in later description. *6 : when the current state is idle and cke = l, bst command will represent deep power down command. refer to ?1. command truth table? and ?3. cke truth table?. *7 : read, reada, writ, writa and bst commands s hould only be issued after the corresponding bank has been activated (actv command) . refer to ? state diagram?. *8 : actv command should only be issued after co rresponding bank has been precharged (pre or pall command) . *9 : required after power up. refer to ?22. power-up initialization? in section ? functional description?. *10 : mrs command should only be issued after all ban ks have been precharged (pre or pall command) . refer to ? state diagram?. function command cke cs ras cas we ba a 10 (ap) address (except for a 10 ) n-1 n device deselect * 5 desl h x h x x x x x x no operation * 5 nop h x lhhhx x x burst stop * 6 , * 7 bst h x l h h l x x x read * 7 read h x l h l h v l column address read with auto-precharge * 7 reada h x l h l h v h column address write * 7 writ h x l h l l v l column address write with auto-precharge * 7 writa h x l h l l v h column address bank active * 8 actv h x l l h h v row address precharge single bank pre h x l l h l v l x precharge all banks pall h x l l h l x h x mode register set * 9 , * 10 mrs hxllllvv v
MB81ES123245-10 7 2. dqm truth table *1 : i = 0, 1, 2, 3 *2 : dqm 0 , dqm 1 , dqm 2 and dqm 3 controls dq 7 to dq 0 , dq 15 to dq 8 , dq 23 to dq 16 , and dq 31 to dq 24 , respectively. 3. cke truth table * 1 *1 : address : a 11 to a 0 @256 page length mode : a 12 to a 0 @128 page length mode : a 13 to a 0 @64 page length mode *2 : the csus command requires that at least one bank is active. refer to ? state diagram?. *3 : ref, self, pd and dpd comm ands should only be issued af ter all banks have been precharged (pre or pall command) . refer to ? state diagram?. *4 : self, pd and dpd commands should only be issued a fter the last read data have been appeared on dq. *5 : cke should be held high during t refc period after t cksp . function symbol cke dqmi *1 , *2 n-1 n data write/output enable enbi * 1 hx l data mask/output disable maski * 1 hx h current state function command cke cs ras cas we ba a 10 (ap) address (except for a 10 ) n-1 n bank active clock suspend mode entry * 2 csushlxxxxxx x any (except idle) clock suspend continue * 2 ? llxxxxxx x clock suspend clock suspend mode exit ? lhxxxxxx x idle auto-refresh command * 3 ref hhlllhxx x idle self-refresh entry * 3 , * 4 selfhllllhxx x self refresh self-refresh exit * 5 selfx lhlhhhxx x lhhxxxxx x idle power down entry * 3 , * 4 pd hllhhhxx x hlhxxxxx x power down power down exit pdx lhlhhhxx x lhhxxxxx x idle deep power down entry * 3 , * 4 dpd h l l h h l x x x deep power down deep power down exit dpdx lhlhhhxx x lhhxxxxx x
MB81ES123245-10 8 4. operation command table (single bank operation) * 1 (continued) current state cs ras cas we address command function idle hxxx x desl nop lhhh x nop l h h l x bst l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa l l h h ba, ra actv bank active after t rcd l l h l ba, ap pre/pall nop * 5 l l l h x ref/self auto-refresh or self-refresh * 3 , * 6 llllmode mrs mode register set (idle after t rsc ) * 3 , * 7 bank active hxxx x desl nop lhhh x nop l h h l x bst l h l h ba, ca, ap read/reada begin read; determine ap l h l l ba, ca, ap writ/writa begin write; determine ap l l h h ba, ra actv illegal * 2 l l h l ba, ap pre/pall begin precharge; determine precharge type lllh x ref/self illegal llllmode mrs read hxxx x desl nop (continue burst to end bank active) lhhh x nop l h h l x bst burst stop bank active l h l h ba, ca, ap read/reada terminate burst, new read; determine ap l h l l ba, ca, ap writ/writa terminate burst, start write; determine ap * 4 l l h h ba, ra actv illegal * 2 l l h l ba, ap pre/pall terminate burst, precharge idle lllh x ref/self illegal llllmode mrs
MB81ES123245-10 9 (continued) current state cs ras cas we address command function write hxxx x desl nop (continue burst to end bank active) lhhh x nop l h h l x bst burst stop bank active l h l h ba, ca, ap read/reada terminate burst, start read; determine ap * 4 l h l l ba, ca, ap writ/writa terminate burst, new write; determine ap l l h h ba, ra actv illegal * 2 l l h l ba, ap pre/pall terminate burst, precharge idle l l l h x ref/self illegal llllmode mrs read with auto- precharge hxxx x desl nop (continue burst to end precharge idle) lhhh x nop l h h l x bst illegal l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa l l h h ba, ra actv l l h l ba, ap pre/pall l l l h x ref/self illegal llllmode mrs write with auto- precharge hxxx x desl nop (continue burst to end precharge idle) lhhh x nop l h h l x bst illegal l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa l l h h ba, ra actv l l h l ba, ap pre/pall l l l h x ref/self illegal llllmode mrs
MB81ES123245-10 10 (continued) ra = row address ba = bank address ca = column address ap = auto precharge current state cs ras cas we address command function precharging h x x x x desl nop (idle after t rp ) lhhh x nop l h h l x bst nop (idle after t rp ) * 8 l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa l l h h ba, ra actv l l h l ba, ap pre/pall nop (pall may affect other bank) * 5 lllh x ref/self illegal llllmode mrs bank activating h x x x x desl nop (bank active after t rcd ) lhhh x nop lhhl x bst l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa l l h h ba, ra actv l l h l ba, ap pre/pall lllh x ref/self illegal llllmode mrs refreshing h x x x x desl nop (idle after t rc ) l h h x x nop/bst nop (idle after t rc ) * 8 lhlx x read/reada/ writ/writa illegal llhx x actv/ pre/pall lllx x ref/self/ mrs mode register setting h x x x x desl nop (idle after t rsc ) lhhh x nop lhhl x bst illegal lhlx x read/reada/ writ/writa llxx x actv/pre/ pall/ref/ self/mrs
MB81ES123245-10 11 *1 : when a command is input, cke should be held high fr om the preceding clock cycle. if any illegal command is asserted, following command operation and data cannot be guaranteed. if the illegal command is input, the power-up initialization is needed again. *2 : illegal to bank in the specified state; entry may be legal in the bank specified by ba, depending on the state of that bank. *3 : illegal if any bank is not idle. *4 : must satisfy bus contention, bus turn around, and/or write recovery requirements. refer to ?7. read interrupted by precharge (example @ bl = 4) ? and ?12. write to read timing (example @ cl = 3, bl = 4) ? in section ? timing diagrams?. *5 : nop to bank precharging or in idle stat e. may precharge bank specified by ba (and ap) . *6 : self command should only be issued af ter the last read data have been appeared on dq. *7 : mrs command should only be issu ed on condition that all dq are in high-z. *8 : bst command should on ly be issued with cke = high.
MB81ES123245-10 12 5. command truth table for cke * 1 (continued) current state cke n-1 cke n cs ras cas we address function self- refresh h x xxxx x invalid l h h x x x x exit self-refresh (self-refresh recovery idle after t rc ) lhlhhh x lhlhhl x illegal lhlhlx x lhllxx x l l x x x x x nop (maintain self-refresh) self- refresh recovery l x xxxx x invalid hhhxxx x idle after t rc hhlhhh x hhlhhl x illegal hhlhlx x hhllxx x hh xxxx x h l xxxx x illegal * 2 power down h x xxxx x invalid lhhxxx x exit power down mode idle lhlhhh x l l xxxx x nop (maintain power down mode) lhllxx x illegal lhlhlx x deep power down h x xxxx x invalid lhhxxx x exit deep power down mode idle * 3 lhlhhh x l l xxxx x nop (maintain deep power down mode) lhllxx x illegal lhlhlx x
MB81ES123245-10 13 (continued) *1 : all entries are specified at cke (n) state. cke in put must satisfy corresponding set up and hold time for cke. *2 : cke should be held high during t refc period. *3 : after deep power down exit, it r equires ?19. deep power down exit? procedure in section ? timing diagrams?. current state cke n-1 cke n cs ras cas we address function bank active bank activating read/write all banks idle hhxxxx x refer to ?4. operation command table?. hlxxxx x refer to ?4. operation command table?. start clock suspend next cycle lxxxxx x invalid precharging refreshing hhxxxx x refer to ?4. operation command table?. hllhhl x illegal hlhxxx x refer to ?4. operation command table?. hlllxx x hllhlx x hllhhh x lxxxxx x invalid clock suspend hxxxxx x invalid l h x x x x x exit clock suspend next cycle l l x x x x x maintain clock suspend any state other than listed above lxxxxx x invalid hhxxxx x refer to ?4. operation command table?. hlxxxx x illegal
MB81ES123245-10 14 functional description 1. sdr i/f fcram basic function this sdr i/f fcrams have major three features of wh ich are the same functions as conventional sdrams : ?synchronized operation?, ?burst mode?, and ?mode re gister? for setting the operation mode. the mb81es123245 are compatible with conventional sdrams regardi ng the basic electrical function and interface. the synchronized operation is the fundamental functi on. an mb81es123245 requires an external clock input (clk) for the synchronization. each operation of mb 81es123245 is determined by commands and all operations function synchronizing with the rising edge of the clock. the burst mode is a very high speed access mode utiliz ing an internal column address generator. once a column addresses for the first access is set, following addresse s are automatically generated by the internal column address counter. the mode register is to justify th e mb81es123245 operation and function in to desired system conditions. refer to ? mode register table?. 2. fcram the mb81es123245 utilizes fcram core technology. the fcram is an acronym of fast cycle random access memory, which provides very fast random cycle time, low latency and low power consumption than conventional sdrams. 3. clock input (clk) and clock enable (cke) all input and output signals of mb81es123245 use register type buffers. a clk is used as a trigger for the registers and internal burst counter increment. all inputs are latched by a rising edge of clk. all outputs are validated by the clk. cke is a high active clock enable signal, and controls an internal clock generator. cke is latched at the rising edge of clk. it is required to se t high one clock cycle before the command input cycle. when cke = low is latched at a clock input during active cycle, the next clock will be internally masked. during idle state (all banks have been precharged) , the power down mode is entered with cke = low and this will make low standby current. the standby current of the d eep power down mode is lower than that of the power down mode. this mode is entered with cke = low, ras = cas = high and we = low. 4. chip select (cs ) cs enables all commands inputs, ras , cas , we , and address input. when cs is high, command signals are negated but internal operation such as burst cycle are not stopped. if such a control isn?t needed, cs can be tied to ground level. 5. command input (ras , cas and we ) unlike a conventional dram, ras , cas , and we do not directly imply mb81es 123245 operation, such as row address strobe by ras . instead, a combination of ras , cas , and we input referring cs input at a rising edge of the clk determines mb81e s123245 operation. refer to ?1. co mmand truth table? in section ? functional truth table.? 6. address input (a 13 to a 0 ) address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. row address field defined by selected page lengt h is as follows : 256 page length = a 11 to a 0 , 128 page length = a 12 to a 0 , 64 page length = a 13 to a 0 . total twenty address input signals by a combination of row address and column address are required to decode a matrix. mb81es123245 adopts an address mu ltiplexer in order to reduce the pin count of the address line. the ro w address is first latched by the bank active command (actv) , and the column address is then latched by a column address strobe command of either the read command (read or reada) or the write command (writ or writa) .
MB81ES123245-10 15 7. bank select (ba 1 , ba 0 ) this mb81es123245 has four banks and ea ch bank is organized as 1 m word s by 32-bit. bank selection by ba occurs at bank active command (actv) followed by re ad (read or reada) , write (writ or writa) , and precharge command (pre) . 8. data i/o (dq 31 to dq 0 ) input data is latched and written into the memory at the clock following the write command input. data output is obtained by the following conditions followed by a read command input : t rac ; time from the bank active command when t rcd (min) is satisfied. (this parameter is reference only.) t cac ; time from the read command when t rcd is greater than t rcd (min) . (this parameter is reference only.) t ac ; time from the rising clock edge after t rac and t cac . the polarity of the output data is identical to that of the input data. data valid period is between access time (determined by the three conditions above) and th e next rising clock edge plus output hold time (t oh ) . 9. input mask/output enable (dqm 3 to dqm 0 ) dqm is an active high enable input and has an out put disable and input mask function. when dqm = high is latched during burst cycle, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by o ne or will go to the next stage depending on burst type. dqm 0 , dqm 1 , dqm 2 , dqm 3 , controls dq 7 to dq 0 , dq 15 to dq 8 , dq 23 to dq 16 , dq 31 to dq 24 , respectively. 10. burst mode operation and burst type the burst mode provides faster memory access. t he burst mode is implemented by keeping the same row address and by automatic strobing colu mn address. access time and cycle time of burst mode is specified as t ac and t ck , respectively. the internal column address counte r operation is determined by a mode register which defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary or full colu mn. in order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required. the burst type can be selected either s equential or interleave mode if burst length is 2, 4 or 8. the sequential mode is an incremental decoding scheme within a boundar y address to be determined by count length, it assigns + 1 to the previous (or initial) address until reaching t he end of boundary address and then wraps round to least significant address ( = 0) . the interleave mode is a scrambled decoding scheme for a 2 and a 0 . if the first access of column address is even (the least si gnificant bit is 0) , the next address will be odd (the least significant bit is 1) , or vice-versa. when the full column burst operati on is executed at single write mode, auto-precharge command is valid only at write operation. current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step mask command (n ormally 3 clock cycles) 2nd step write command after l owd burst write burst write write command burst write burst read read command burst read precharge precharge command burst write precharge precharge command
MB81ES123245-10 16 11. full column burst and burst stop command (bst) the full column burst is an option of burst length and av ailable only at sequential mode of burst type. this full column burst mode executes by automatically strobing the column address while keeping the same row address. if burst mode reaches the end of column address, then it wraps ar ound to the first column address ( = 0) and continues to count until interrupted by the new read (read) /write (writ) , precharge (pre) , or burst stop (bst) commands. the selection of au to-precharge option is illegal dur ing the full column burst operation. the bst command is applicable to terminate the burs t operation. if the bst command is asserted during the burst mode, its operation is terminated immediatel y and the internal state moves to bank active. when a read mode is interrupted by the bst command, t he output will be in high-z. for the detailed rule, please refer to ?8. read interrupted by burst stop (example @cl = 3, bl = full column? in section ? timing diagrams?. when a write mode is interrupted by the bst comman d, the data to be input at the same time with the bst command will be ignored. 12. burst read & single write the burst read and single write mode provides single word write operation regardless of its burst length. in this mode, burst read operation does not be affected by this mode. 13. programmable page length function the programmable page length function provides lower operation current than regul ar sdram. page length is selected by mode register set, and the composition of the row address field and column address field are defined for selected page length as below. burst length starting column address a 2 a 1 a 0 sequential mode interleave mode 2 x x 0 0 ? 10 ? 1 x x 1 1 ? 01 ? 0 4 x 0 0 0 ? 1 ? 2 ? 30 ? 1 ? 2 ? 3 x 0 1 1 ? 2 ? 3 ? 01 ? 0 ? 3 ? 2 x 1 0 2 ? 3 ? 0 ? 12 ? 3 ? 0 ? 1 x 1 1 3 ? 0 ? 1 ? 23 ? 2 ? 1 ? 0 8 0 0 0 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 70 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 0 0 1 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 01 ? 0 ? 3 ? 2 ? 5 ? 4 ? 7 ? 6 0 1 0 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 0 ? 12 ? 3 ? 0 ? 1 ? 6 ? 7 ? 4 ? 5 0 1 1 3 ? 4 ? 5 ? 6 ? 7 ? 0 ? 1 ? 23 ? 2 ? 1 ? 0 ? 7 ? 6 ? 5 ? 4 1 0 0 4 ? 5 ? 6 ? 7 ? 0 ? 1 ? 2 ? 34 ? 5 ? 6 ? 7 ? 0 ? 1 ? 2 ? 3 1 0 1 5 ? 6 ? 7 ? 0 ? 1 ? 2 ? 3 ? 45 ? 4 ? 7 ? 6 ? 1 ? 0 ? 3 ? 2 1 1 0 6 ? 7 ? 0 ? 1 ? 2 ? 3 ? 4 ? 56 ? 7 ? 4 ? 5 ? 2 ? 3 ? 0 ? 1 1 1 1 7 ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 67 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 ? 0 row address column address 256 page length a 11 to a 0 a 7 to a 0 128 page length a 12 to a 0 a 6 to a 0 64 page length a 13 to a 0 a 5 to a 0
MB81ES123245-10 17 row/column address allocation at each page length is shown as the following table. for example, a 13 (row address) at 64 page length mode is corresponded to a 6 (column address) at 128 page length mode. 14. precharge and precharge option (pre, pall) the mb81es123245 memory core is the same as conv entional sdrams, requiring precharge and refresh operations. precharge rewrites the bit line and resets the internal row address line. with the precharge command (pre) , mb81es123245 will automatically be in a standby state after precharge time (t rp ) . the precharged bank is selected by combination of ap and ba when precharge command is asserted. if ap = high, all banks are precharged regardless of ba (pall command) . if ap = low, a bank to be selected by ba is precharged (pre command) . the auto-precharge enters precharge mo de at the end of burst mode of read or write without precharge command assertion. this au to-precharge is entered by setting ap = high when a read or write command is asserted. refer to ?1. command truth table? in section ? functional truth table?. 15. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the mb81es123245 auto-refresh command (ref) generates precharge command internally. all banks of mb81es123245 should be precharged prior to asserting the auto-refresh command. the auto-refresh command should also be asserted every 15.6 s or a total 4,096 refresh commands within every 64 ms period to ensure data stored. 16. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh function until cancelled by the self-refresh exit command (selfx) . the self-refresh is entered by applying an auto-refresh command in conjunction with cke = low (self) . once mb81es123245 enters the self-refresh mode, all inputs except fo r cke will be in a ?don?t care? state (high or low) and all outputs will be in a high-z state. during the self-refresh mode, cke = low should be maintained. self command should only be issued after last read data has been appeared on dq. note : when the burst refresh method is used, a total of 4,096 auto-refresh co mmands within 2 ms must be asserted prior to the self-refresh mode entry. 17. self-refresh exit (selfx) to exit self-refresh mode, apply the self-re fresh exit command (selfx) after minimum t cksp from cke brought high. after selfx, the no operation command (nop) or the deselect command (d esl) should be asserted during t refc period. cke should be held high during t refc period after t cksp . refer to ?16. self-refresh entry and exit? in section ? timing diagrams? for the detail. it is recommended to assert the auto-refresh command just after the t refc period to prevent row addresses not to be refreshed. note : when the burst refresh method is used, a total of 4,096 auto-refresh co mmands within 2 ms must be asserted after the self-refresh exit. 64 page length row : a 13 to a 0 column : a 5 to a 0 012345678910111213543210 128 page length row : a 12 to a 0 column : a 6 to a 0 01234567891011126543210 256 page length row : a 11 to a 0 column : a 7 to a 0 0123456789101176543210
MB81ES123245-10 18 18. mode register set (mrs) the mode register of mb81es123245 provides a variety of different operations. the register consists of five operation fields : burst length, burst type, cas la tency, operation code and page length. refer to ? mode register table?. the mode register can be progra mmed by the mode register set command (mrs) . once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command. mrs command should only be issued on condition that all dq is in high-z. the condition of the mode register is undefined after the power-up stage. set each fi eld after initialization of this device. refer to ?22. power-up initialization?. 19. extended mode register set (emrs) the extended mode register consists of two operation fields : partial array self refresh (pasr) and driver strength (ds) . refer to ? mode register table?. the state of the extended mode register is undefined after the power-up stage. set each field after initia lization. refer to ?22. power-up initialization?. 20. partial array self-refresh (pasr) partial array self-refresh is a function that limits the memory array size to be refreshed during self-refresh in order to reduce the self-refresh current. data outside the defined area will not be retained. 21. driver strength (ds) this function is to adjust the driver strength of the data output. 22. power-up initialization the state of mb81es123245 internal conditions after power-up will be undefined. follow the following power on sequence to execute read or write operation. 1. apply power (v dd should be applied before or in parallel with v ddq ) and start clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, and nop condition for a minimum of 300 s. 3. precharge all banks by single bank precharge comm and (pre) or all banks precharge command (pall) . 4. assert minimum of 2 auto-refresh commands (ref) . 5. program the mode register by mode register set command (mrs) . 6. program the extended mode register by ex tended mode register set command (emrs) . in addition, it is recommended dqm and cke track v dd to insure that output is hi gh-z state. the mode register set command (mrs) and extended mode register set command (emrs) can al so be set before 2 auto-refresh commands (ref) . 23. automatic temperature compensated self-refresh (atcsr) the mb81es123245 has an atcsr feature for low-po wer self-refresh current at room temperature.
MB81ES123245-10 19 state diagram self selfx ref cke mrs emrs cke\ (dpd) cke(dpdx) cke\ (pd) actv cke\ (csus) cke bst bst writ writ read read cke cke cke cke writa writa writa reada read reada reada writ cke\ (csus) cke\ (csus) cke\ (csus) cke\ (csus) pre or pall pre or pall pre or pall pre or pall mode register set self refresh idle read suspend bank active auto refresh power down bank active suspend write write suspend power on precharge read write with auto precharge read with auto precharge power applied definition of allows automatic sequence read suspend write suspend note : cke\ means cke goes low-level from high-level. extended mode register set deep power down manual input
MB81ES123245-10 20 bank operation command table minimum clock latency or delay time for single bank operation ? : illegal command *1 : if t rp (min) < cl t ck , minimum latency is a sum of (bl + cl) t ck . *2 : assume all banks are in idle state. *3 : assume output is in high-z state. *4 : assume t ras (min) is satisfied. *5 : assume no i/o conflict. *6 : assume after the last data have been appeared on dq. *7 : if t rp (min) < (cl ? 1) t ck , minimum latency is a sum of (bl + cl ? 1) t ck . mrs actv read * 4 reada writ * 4 writa pre pall ref self bst mrs t rsc t rsc ???? t rsc t rsc t rsc t rsc t rsc actv ?? t rcd t rcd t rcd t rcd t ras t ras ?? 1 read ?? 11 * 5 1 * 5 1 * 4 1 * 4 1 ?? 1 reada * 1 , * 2 bl + t rp bl + t rp ???? * 4 bl + t rp * 4 bl + t rp * 2 bl + t rp * 2 , * 7 bl + t rp ? writ ?? t wr t wr 11 * 4 t dpl * 4 t dpl ?? 1 writa * 2 bl ? 1 + t dal bl ? 1 + t dal ???? * 4 bl ? 1 + t dal * 4 bl ? 1 + t dal * 2 bl ? 1 + t dal * 2 bl ? 1 + t dal ? pre * 2 , * 3 t rp t rp ???? 1 * 4 1 * 2 t rp * 2 , * 6 t rp 1 pall * 3 t rp t rp ???? 11t rp * 6 t rp 1 ref t rc t rc ???? t rc t rc t rc t rc t rc selfx t rc t rc ???? t rc t rc t rc t rc t rc second command (same bank) first command
MB81ES123245-10 21 minimum clock latency or delay time for multi bank operation ? : illegal command *1 : if t rp (min) < cl t ck , minimum latency is a sum of (bl + cl) t ck . *2 : assume bank of the ob ject is in idle state. *3 : assume output is in high-z state. *4 : t rrd (min) of other bank (second comm and will be asserted) is satisfied. *5 : assume other bank is in active, read or write state. *6 : assume t ras (min) is satisfied. *7 : assume other banks are not in reada/writa state. *8 : assume after the last data have been appeared on dq. *9 : if t rp (min) < (cl ? 1) t ck , minimum latency is a sum of (bl + cl ? 1) t ck . *10 : assume no i/o conflict. mrs actv * 5 read * 5, * 6 reada * 5 writ * 5 , * 6 writa pre pall ref self bst mrs t rsc t rsc ???? t rsc t rsc t rsc t rsc t rsc actv ? * 2 t rrd * 7 1 * 7 1 * 7 1 * 7 1 * 6 , * 7 1 * 7 t ras ?? 1 read ? * 2 , * 4 1 11 * 10 1 * 10 1 * 6 1 * 6 1 ?? 1 reada * 1 , * 2 bl + t rp * 2 , * 4 1 * 6 1 * 6 1 * 6 , * 10 1 * 6 , * 10 1 * 6 1 * 6 bl + t rp * 2 bl + t rp * 2 , * 9 bl + t rp ? writ ? * 2 , * 4 1 1111 * 6 1 * 6 t dpl ?? 1 writa * 2 bl ? 1 + t dal * 2 , * 4 1 * 6 1 * 6 1 * 6 1 * 6 1 * 6 1 * 6 bl ? 1 + t dal * 2 bl ? 1 + t dal * 2 bl ? 1 + t dal ? pre * 2 , * 3 t rp * 2 , * 4 1 * 7 1 * 7 1 * 7 1 * 7 1 * 6 , * 7 1 * 7 1 * 2 t rp * 2 , * 8 t rp 1 pall * 3 t rp t rp ???? 11t rp * 8 t rp 1 ref t rc t rc ???? t rc t rc t rc t rc t rc selfx t rc t rc ???? t rc t rc t rc t rc t rc second command (other bank) first command
MB81ES123245-10 22 mode register table ? mode register set ba 1 ba 0 a 13 *5 a 12 *4 a 11 a 10 a 9 a 8 *3 a 7 *3 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address 0 0 pl 0 0 opcode 0 0 cl bt bl mode register a 6 a 5 a 4 cas latency 000 reserved 001 reserved 010 2 011 3 100 reserved 101 reserved 110 reserved 111 reserved a 2 a 1 a 0 burst length bt = 0 bt = 1 *2 0 0 0 1 reserved 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 111 full column reserved a 13 a 12 page length gnd gnd 256 page gnd 1 128 page 1 0 64 page 11reserved a 3 burst type 0 sequential (wrap round, binary-up) 1 interleave (wrap round, binary-up) a 9 operation code 0 burst read & burst write 1 burst read & single write *1 ? extended mode register ba 1 ba 0 a 13 *5 a 12 *4 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address 100 000 000 ds 00 pasr extended mode register a 6 a 5 driver strength 00 100 % (normal) 01 70 % 10 60 % 11 30 % a 2 a 1 a 0 self refresh area 0 0 0 128 m bit 001 64 m bit (ba 1 = 0) 010 reserved 011 reserved 100 reserved 101 reserved 110 reserved 111 reserved *1. when a 9 = 1, burst length at write is always one regardless of bl value. *2. bl = 1 and full column are not applic able to the interleave mode. *3. a 7 = 1 and a 8 = 1 are reserved for vendor test. *4. a 12 should be connected to gn d at 256 page length mode. *5. a 13 should be connected to gnd at 128 and 256 page length mode.
MB81ES123245-10 23 absolute maximum ratings * : all voltages are referenced to v ss . warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. recommended operating conditions *3 : the maximum junction temperature of fcram (tj) should not be more than + 95 c. tj is represented by the power consumption of fcram (p fcram ) and logic lsi (p d ) , the thermal resistance of the package ( ja) , and the maximum ambient te mperature of the sip (tamax) . pmax[w] = p fcram + p d tjmax[ c] = tamax[ c] + ja[ c/w] pmax[w] warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max supply voltage* v dd , v ddq ? 0.5 + 2.6 v input/output voltage* v in , v out ? 0.5 + 2.6 v short circuit output current i out ? 50 + 50 ma power dissipation p d ? 1.0 w storage temperature t stg ? 55 + 125 c parameter symbol value unit min typ max supply voltage v dd , v ddq 1.7 1.8 1.9 v v ss , v ssq 000 v input high voltage * 1 v ih v ddq 0.8 ? v ddq + 0.3 v input low voltage * 2 v il ? 0.3 ? v ddq 0.2 v junction temperature * 3 tj ? 25 ? + 95 c 2.6 v v ih v il v ih min ? 1.0 v v il v ih v il max *1 : overshoot limit : v ih (max) = 2.6 v for pulse width 5 ns, pulse width measured at 50 % of pulse amplitude. *2 : undershoot limit : v il (min) = v ssq ? 1.0 v for pulse width 5 ns, pulse width measured at 50 % of pulse amplitude. 50 % of pulse amplitude pulse width 5 ns 50 % of pulse amplitude pulse width 5 ns
MB81ES123245-10 24 capacitance (t a = + 25 c, f = 1 mhz) parameter symbol min typ max unit input capacitance, except for clk c in1 1.5 ? 3.0 pf input capacitance for clk c in2 1.5 ? 3.0 pf i/o capacitance c i / o 2.0 ? 4.0 pf
MB81ES123245-10 25 dc characteristics (at recommended operating conditi ons unless otherwise noted.) * 1 , * 2 , * 3 (continued) parameter symbol condition value unit min max output high voltage v oh ( dc ) i oh = ? 0.1 ma v ddq ? 0.2 ? v output low voltage v ol ( dc ) i ol = 0.1 ma ? 0.2 v input leakage current i li 0 v v in v ddq , all other pins not under test = 0 v ? 5 + 5 a output leakage current i lo 0 v v in v ddq , data out disabled ? 5 + 5 a operating current (average power supply current) i dd1 burst length = 1, t rc = min, t ck = min, one bank active, output pin open, address changed up to 1 time during t rc (min) , 0 v v in v il (max) , v ih (min) v in v dd 256 page length ? 60 ma 128 page length ? 45 64 page length ? 35 precharge standby current (power supply current) i dd2p cke = v il , all banks idle, t ck = min, power down mode, 0 v v in v il (max) , v ih (min) v in v dd ? 0.8 ma i dd2ps cke = v il , all banks idle, clk = v ih or v il , power down mode, 0 v v in v il (max) , v ih (min) v in v dd ? 0.5 ma i dd2n cke = v ih , all banks idle, t ck = 20 ns, nop commands only, input signals (except for commands) are changed 1 time during 2 clocks, 0 v v in v il (max) , v ih (min) v in v dd ? 10 ma i dd2ns cke = v ih , all banks idle, clk = v ih or v il , input signals are stable, 0 v v in v il (max) , v ih (min) v in v dd ? 1ma burst mode current (average power supply current) i dd4 t ck = min, burst length = 4, output pin open, all-banks active, gapless data, 0 v v in v il (max) , v ih (min) v in v dd cl = 2 ? 40 ma cl = 3 ? 70 refresh current#1 (average power supply current) i dd5 auto-refresh, t ck = min, t rc = min, 0 v v in v il (max) , v ih (min) v in v dd ? 150 ma
MB81ES123245-10 26 (continued) (at recommended operating conditi ons unless otherwise noted.) * 1 , * 2 , * 3 *1 : all voltages are referenced to v ss . *2 : dc characteristics are measured after following t he ?22. power-up initializati on? procedure in section ? functional description.? *3 : i dd depends on the output termination or load condition, clock cycle rate, signal clocking rate. the specified values are obtained with t he output open and no termination resistor. parameter symbol condition value unit min max refresh current #2 (average power supply current) i dd6 self-refresh (128m-bit) , t ck = min, cke 0.2 v, 0 v v in v il (max) , v ih (min) v in v ddq tj + 35 c ? 200 a tj + 95 c ? 800 precharge standby current in deep power down mode i dd7 cke 0.2 v, all banks idle, deep power down mode, 0 v v in v il (max) , v ih (min) v in v dd ? 15 a
MB81ES123245-10 27 ac characteristics 1. basic ac characteristics (at recommended operating conditi ons unless otherwise noted.) * 1 , * 2 , * 3 *1 : ac characteristics are measured after following t he ?22. power-up initialization? procedure in section ? functional description?. *2 : ac characteristics assume t t = 1 ns, 50 ? of termination resistor. refer to ?5. measurement condition of ac characteristics?. *3 : 0.9 v is the reference level for 1.8 v i/o for measur ing timing of input/output signals. transition times are measured between v ih (min) and v il (max) . *4 : this value is for reference only. *5 : if input signal transition time (t t ) is longer than 1 ns : [ (t t /2) ? 0.5] ns should be added to t ac (max) , t hz (max) , and t cksp (min) spec values, [ (t t /2) ? 0.5] ns should be subtracted from t lz (min) , t hz (min) , and t oh (min) spec values, and (t t ? 1.0) ns should be added to t ch (min) , t cl (min) , t si (min) , and t hi (min) spec values. *6 : t ac also specifies the access time at burst mode. *7 : t ac and t oh are measured under output load circuit sh own in ?5. measurement condition of ac characteristics?. *8 : specified where output buffer is no longer driven. *9 : auto refresh command is allowed to input maximum 32 times a t refi (max) period. parameter symbol value unit min max clock period cl = 2t ck2 18.5 ? ns cl = 3t ck3 9.2 ? ns clock high pulse width * 5 t ch 3 ? ns clock low pulse width * 5 t cl 3 ? ns input setup time * 5 t si 2.5 ? ns input hold time * 5 t hi 1 ? ns access time from clk (t ck = min) * 5 , * 6 , * 7 cl = 2t ac2 ? 9ns cl = 3t ac3 ? 7ns clk to output in low-z delay time * 5 t lz 0 ? ns clk to output in high-z delay time * 5 , * 7 , * 8 cl = 2t hz2 2.5 9 ns cl = 3t hz3 2.5 7 ns output hold time * 4 t oh 2.5 ? ns time between auto-refresh command interval * 9 t refi ? 15.6 s time between refresh t ref ? 64 ms refresh cycle time t refc 82.8 ? ns transition time t t 0.5 10 ns cke setup time for power down exit * 5 t cksp 2.5 ? ns
MB81ES123245-10 28 2. base values for clock count/latency * : actual clock count of t rc (l rc ) will be sum of clock count of t ras (l ras ) and t rp (l rp ) . 3. clock count formula note : all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by above formula. 4. latency (the latency values on these paramete rs are fixed regardless of clock period.) parameter symbol value unit min max ras cycle time *t rc 82.8 ? ns ras precharge time t rp 24 ? ns ras active time t ras 55.2 110000 ns ras to cas delay time t rcd 24 ? ns write recovery time t wr 9.2 ? ns ras to ras bank active delay time t rrd 16 ? ns data-in to precharge lead time t dpl 18.4 ? ns data-in to active/refresh command period cl = 2t dal2 1 cyc + t rp ? ns cl = 3t dal3 2 cyc + t rp ? ns mode register set cycle time t rsc 16 ? ns parameter symbol value unit cke to clock disable l cke 1cycle dqm to output in high-z l dqz 2cycle dqm to input data delay l dqd 0cycle last output to write command delay l owd 2cycle write command to input data delay l dwd 0cycle precharge to output in high-z delay cl = 2l roh2 2cycle cl = 3l roh3 3cycle burst stop command to output in high-z delay cl = 2l bsh2 2cycle cl = 3l bsh3 3cycle cas to cas delay (min) l ccd 1cycle cas bank delay (min) l cbd 1cycle clock (round up a whole number) base value clock period
MB81ES123245-10 29 5. measurement condition of ac characteristics 6. setup, hold and delay time output c l r = 50 ? v dd 0.5 0.9 v 0.9 v 1.44 v 1.44 v 0.36 v 0.36 v 0.9 v t ck t ch t si t hi t ac t lz t hz t oh t cl clk iutput (control, address, and data) output note : reference level of input signal is 0.9 v. access time is measured at 0.9 v. ac characteristics are also measured in this condition.
MB81ES123245-10 30 7. delay time for power down exit 8. pulse width clk h or l t cksp (min) 1 clock (min) h or l cke command nop nop actv t rc , t rp , t ras , t rcd , t wr , t ref , t refc , t dpl , t dal , t rsc , t rrd , t cksp clk command command input (control) note : these parameters are a limit value of the rising edge of the clock from one command input to next input. t cksp is the latency value from the rising edge of cke. measurement reference voltage is 0.9 v.
MB81ES123245-10 31 9. access time clk q (valid) q (valid) q (valid) command dq 31 to dq 0 (output) read (cas latency ? 1) t ck t ac t ac t ac
MB81ES123245-10 32 timing diagrams 1. clock enable read and write suspend (@ bl = 4) 2. power down entry and exit i cke l cke clk (1 clock) (1 clock) (no change) not written not written (no change) cke clk (internal) dq 31 to dq 0 (read) dq 31 to dq 0 (write) d1 d2 d3 d4 q1 q2 q3 q4 ? 1 ? 1 ? 2 ? 2 ? 3 ? 3 *1 : the latency of cke (l cke ) is one clock. *2 : during read mode, the burst counter is not be in cremented at the following clock of csus command. the output data remain the same. *3 : during write mode, the data at the fo llowing clock of csus command is ignored. clk cke command nop pd (nop) ? 2 nop t cksp (min) t ref (max) 1clock (min) pdx h or l actv ? 4 ? 3 ? 1 *1 : precharge command (pre or pall) should be assert ed if any bank is active and in the burst mode. *2 : precharge command can be posted in conjunction with cke after the last read data have been appeared on dq. *3 : it is recommended to apply no p command in conjunction with cke. *4 : the actv command can be latched after t cksp (min) + 1 clock (min) .
MB81ES123245-10 33 3. column address to column address input delay 4. different bank address input delay clk address (1 clock) ras cas i ccd i ccd i ccd i ccd row address column address column address column address column address column address t rcd (min) note : cas to cas delay (l ccd ) can be one or more clock period. clk ras cas ba address row address bank 0 bank 0 bank 1 bank 1 (1 clock) bank 0 i cbd t rcd (min) t rcd (min) t rrd (min) row address column address column address column address note : cas bank delay (l cbd ) can be one or more clock period.
MB81ES123245-10 34 5. input mask and output disable (@ bl = 4) 6. precharge timing (applied to the same bank) clk dqm 3 to dqm 0 (@ read) dqm 3 to dqm 0 (@ write) dq 31 to dq 0 (@ write) dq 31 to dq 0 (@ read) d1 q1 q2 masked i dqz (2 clocks) high-z q4 end of burst end of burst d4 d3 i dqd (same clock) clk command actv t ras (min) pre ? * : pre means ?pre? or ?pall?.
MB81ES123245-10 35 7. read interrupted by precharge (example @ bl = 4) command command command no effect (end of burst) clk dq 31 to dq 0 dq 31 to dq 0 dq 31 to dq 0 pre ? 2 high-z high-z high-z q1 q2 q1 q2 q1 q2 q3 q4 pre ? 2 pre ? 2 q3 i roh (3 clocks) *1 i roh (3 clocks) *1 *1 : in case of cl = 3, the latency from the precharge command (pre) to output in high-z (l roh ) is 3 clocks. *2 : pre means ?pre? or ?pall?.
MB81ES123245-10 36 8. read interrupted by bu rst stop (example @cl = 3, bl = full column) 9. write interrupted by burst stop (example @ bl = 2) bst q n + 1 i bsh (3 clocks) command bst q n q n ? 2 q n ? 1 q n + 2 high-z clk dq 31 to dq 0 clk command dq 31 to dq 0 last data input masked by bst bst writ
MB81ES123245-10 37 10. write interrupted by precharge (example @ cl = 3, bl = 4) 11. read interrupted by write (example @ cl = 3, bl = 4) clk command dq 31 to dq 0 t dpl (min) t rp (min) d1 d2 masked by pre pre* 1, * 2 writ actv *1 : the precharge command (pre) should only be issued after the t dpl of final data input is satisfied. *2 : pre means ?pre? or ?pall?. clk command dqm 3 to dqm 0 dq 31 to dq 0 read writ i dqz (2 clocks) masked q1 d1 d2 i owd (2 clocks) i dwd (same clock) ? 1 ? 2 ? 3 *1 : first dqm makes high-z state bet ween last output and first input data. *2 : second dqm makes internal output data mask to avoid bus contention. *3 : third dqm also makes internal output data mask. if burst read ends (final data output) at or after the second clock of burst write, this third dqm is required to avoid internal bus contention.
MB81ES123245-10 38 12. write to read timing (example @ cl = 3, bl = 4) 13. read with auto-precharge (exaple @ cl = 3, bl = 2, applied to same bank) dqm 3 to dqm 0 writ read (cl ? 1) t ck d1 d2 q3 q2 q1 clk command dq 31 to dq 0 d3 masked by read t ac (max) t wr (min) note : read command should be issued after t wr of final data input is satisfied. *1 : precharge at read with auto-precharge command (reada ) is started from number of clocks that is the same as burst length (bl) afte r the reada command is asserted. *2 : next actv command should be issued after bl + t rp (min) from reada command. actv clk actv nop reada ? 1, ? 2 dq 31 to dq 0 dqm 3 to dqm 0 q1 q2 command t ras (min) t rp (min) bl + t rp (min) ? 2 2 clocks *1 (same value as bl)
MB81ES123245-10 39 14. write with auto-precharge (example @ cl = 3, bl = 2, applied to same bank) * 1 , * 2 , * 3 15. auto-refresh clk actv dq 31 to dq 0 dqm 3 to dqm 0 actv writa nop d1 d2 command bl + 1 + t rp (min) *5 t ras (min) t dal (min) 2 clocks *4 *1 : even if the final input data are masked by dqm, the precharge is started at same timing as the case final data are not masked. *2 : once auto precharge command is asserted, no new command within the sa me bank can be issued. *3 : auto-precharge command doesn?t affect at full colu mn burst operation except burst read & single write. *4 : precharge at write with auto-prec harge is started after 1 clock at cl = 2, 2 clocks at cl = 3 from the end of burst. *5 : next command should be issued after bl + t rp (min) at cl = 2, bl + 1 + t rp (min) at cl = 3 from writa command. ref ? 1 h or l ? 2 h or l ? 2 ref nop ? 3 t refc (min) t refc (min) nop ? 3 command ? 4 clk command ba ba *1 : all banks should be precharged prior to the first auto-refresh command (ref) . *2 : bank select is ignored at ref command. the refr esh address and bank select are selected by internal refresh counter. *3 : either nop or desl command should be asserted during t refc period while auto-refresh mode. *4 : any activation command such as actv or mr s command other than ref command should be asserted after t refc from the last ref command.
MB81ES123245-10 40 16. self-refresh entry and exit 17. mode register set nop ? 1 ? 5 self h or l h or l t si (min) t cksp (min) t refc (min) *4 selfx command nop ? 3 nop ? 2 clk cke command *1 : precharge command (pre or pall) should be asse rted if any bank is active prior to self-refresh entry command (self) . *2 : the self-refresh exit co mmand (selfx) is latched after t cksp (min) . it is recommended to apply nop command on the rising edge of cke. *3 : either nop or desl command can be asserted during t refc period. *4 : cke should be held high during t refc period after t cksp . *5 : cke level should be held less than 0.2 v during self-refresh mode. actv mrs or emrs mode row address nop t rsc (min) clk command address note : the mode register set command (mrs) or ex tended mode register set command (emrs) should only be asserted after all banks have been precharged.
MB81ES123245-10 41 18. deep power down entry 19. deep power down exit nop h or l h or l t si (min) dpd clk cke command note : deep power down entry command (dpd) should only be asserted if all banks have been precharged and all outputs are in high-z. nop h or l t cksp (min) t rsc (min) t rsc (min) t rp (min) t refc (min) t refc (min) nop 300 s (min) pall ref ref mrs emrs dpdx clk cke command actv
MB81ES123245-10 f0612 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

▲Up To Search▲

Price & Availability of MB81ES123245-10

	To Download MB81ES123245-10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .